J'ai passé un entretien chez Xilinx (Santa Clara, CA)
Entretien
Introduce job responsibility, ask simple questions related to your resume, more questions on FPGA IP verification, including xdc, verilog, timing constraints, etc. that you can learn from master of electrical engineering / digital design courses.
Questions d'entretien [1]
Question 1
Explain set_multicycle_path, how to change start clock, end clock
My resume was floated by a known contact. I had not applied for the position. Since my skills matched with what they were looking for I got a call. The interview was basic, just questions on my resume. But did not receive any response after that. I emailed the manager who took my interview, but she didn't respond and I finally gave up.
Questions d'entretien [1]
Question 1
A question on FIFO depth and Constrained Random Verification