Interviewed with PCIe team. Female engineer from Colorado asked me a reasonable nested loop question then proceeded to interrupt me at least 8 times. After the 5th interruption I gave up solving the problem and did my best not to make a scene. She continued to interrupt me then asked very condescending questions in a very sarcastic tone. I have never met, seen, or heard of a more disrespectful interviewer during my time as a professional engineer. I later met an engineer from Xilinx (Malaysia) who worked with this woman and confirmed my assessment of her. In my opinion there was an additional engineer who was insulting. He asked me very simple questions then finished with a trick question that I didn't realize until the interview was over. I'm certain that I have designed more async interfaces than the entire team combined but I'm sure he told everyone that I missed the trick async question since he insisted on taking a picture of my solution. They were typical arrogant engineers. I couldn't be more please to not be working for this team. Lastly, the position was for a SystemVerilog OVM verification engineer working on PCIe gen 3. NOT one single question on systemverilog, OVM, or PCIe. Not one.

The interview process involved a telephonic interview and a face to face interview. They asked briefly about my qualification and skills in the telephonic Interview. In the face to face interview the technical round was involved with asking few questions on coding in verilog and system verilog.