3 rounds of interview
2 technical [ 45 min each ] + 1 Hr round [ 30 min ]
Puzzle from GFG
Digital electronics
Verilog
Digital IC design
Sequence detector
Clock divide circuits
CDC, Metastability
Pipelining, Hazards
Questions d'entretien [1]
Question 1
Questions were
FSM , types
Draw 10X11 sequence detector using mealy and more machine
Verilog code for FSM
Fifo
FIFO depth calculation