J'ai postulé en ligne. Le processus a pris 1 semaine. J'ai passé un entretien chez Qualcomm (San Diego, CA) en oct. 2016
Entretien
One telephonic round, Six onsite interview rounds and one post onsite telephonic interview. They tested the basics of vlsi design, RTL design, system verilog, verilog, programming,digital design, etc. Since the position is for verification, they asked me the basics of system verilog and verilog quiet a lot.
J'ai postulé via la recommandation d'un employé. J'ai passé un entretien chez Qualcomm en mai 2026
Entretien
Applied through a manager via linkedin and applied on the website as well. screening interview happened but they rejected after the screening round with a staff engineer. It took one week.
Questions d'entretien [1]
Question 1
They asked me about my experience, projects, then basic digital electronics questions like draw 2x1 mux using tri-state buffers. draw 3:1 AND gate using 4x1 mux. then asked me about UVM, AHB, assertions
J'ai postulé en ligne. Le processus a pris 3 semaines. J'ai passé un entretien chez Qualcomm (Raleigh, NC) en juin 2015
Entretien
First 1:1 phone interview, Then an on site interview. In the onsite interview, three technical interviews separately in the morning, then having lunch with manager. In the afternoon, another technical interview and then talked with the manager of the manager.
Questions d'entretien [1]
Question 1
First interviewer did bus connection verification. so he asked about the protocol of ahb and axi. Then he asked how many vip should be used for their verification environment. I didn't understand the question clearly. Because if we want to keep CPU and the code run on real CPU, we don't need to replace these interfaces with VIPs, but if the CPU needs to be replaced, only other slave/master interfaces need to be replaced by VIPs. After he cleared it, what he wanted to do was to replace all the CPU interfaces and other IP interfaces.
The second interviewer asked 2 questions: 1) how to check the module was reset by reading/writing registers? The premise for this was there was no spec for register. 2) how to check an interrupt was generated? There was a bit in the register for the interrupt signal.
The third interviewer asked the following questions: 1) virtual memory structure 2) spin lock 3) tomasulo 4) fibonacci generator
The last technical interviewer asked: 1) shell questions: search a key word in a file and count how many lines contain the key word 2) Perl sort question: user perl to sort a hash with key or with value 3) set environment variable in Perl 4) fibonacci generator 5) there are 2 buckets: 5 litters and 3 litters, how to get 4 litters of water 6) there is a rectangle pie, remove a small rectangle in that large rectangle, after that, use a straight line to cut the pie to get 2 equal areas.
There was another question I forgot who asked: use SystemVerilog to generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) ...