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      Entretien pour Design and Verification Engineer

      19 août 2022
      Candidat à l'entretien anonyme
      Hyderâbâd

      Autres retours d’entretien d’embauche pour un poste comme Design and Verification Engineer chez Intel Corporation

      Entretien pour Design Verification Engineer

      13 mai 2026
      Candidat à l'entretien anonyme
      Bengaluru
      Aucune offre
      Aucune offre
      Expérience neutre
      Entretien difficile

      Candidature

      J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Intel Corporation (Hyderâbâd) en août 2022

      Entretien

      I have attended this recruitment via a referral. I was invited to take this test at their office in Hyderabad. First step was to write a written test. The written test consisted of Basic Digital Design concepts, Verilog , a question from analog and a question from unix. Out of 25 questions, 10 were multiple choice questions and 15 were of descriptive nature. After getting selected for the interview round, three rounds of interview took place. These three rounds were of technical nature. Each round lasted around 50 minutes to 1 hour. As I struggled in the interview process, the third round lasted around 25 minutes. The interview process was about testing the basics of digital design. It was about the way in which we solve or approach the problem. They asked about concepts of multiplexer, flip flops, latches, counters , shift register to name a few. They have also asked about Verilog. My performance was not good as I was unable to answer questions related to Verilog. They have also asked whether I took training from VLSI training institutes too. The three rounds of interview were of technical in nature. Each round consisted of a panel of two members.

      Questions d'entretien [1]

      Question 1

      ( I have just passed out from BTech) First round: 1) Asked about college. 2) Implement 7:1 Mux using 2:1 mux 3) Why verilog is used in this field? 4) Difference between latch and flip flop ( with waveforms). 5) You had C in engineering, why didn't you include it in your resume? C has more use , right? 6) About Major Project ( Why it is not related to VLSI?) 7) Frequency Division Circuit 8) What is the default value of wire? 9) What is the default value of reg? 10 ) Convert one hexadecimal number to binary Second Round 1) Tell me about yourself. ( I was enrolled in a program, asked about that program in detail.) 2) Design an asynchronous flipflop in verilog. 3) What is setup time, hold time? 4) What are the different types of delay and explain them? 5) Differences between RISC and CISC. 6) What are the application of counters? 7) What is a shift register explain its operation with a suitable circuit diagram? 8) Psuedo code for finding prime numbers from 1 to 100. 9) What is LSFR? 10) What is pipelining how it is implemented? 11) Could you draw the symbol of CMOS inverter? 12) What is CMOS? 13) Do you really know python? 14) What did you do in MATLAB? 15) Certifications are not enough, did you do any project related to this? Third Round: 1) Gave an AND OR circuit and asked to convert it into a MUX. 2) Difference between latch and flipflop 3) Draw a latch using only NAND gates. 4) Draw a D latch. 5) Psuedocode for checking a string in a the contents of a file in a directory of files. 6) Is MATLAB a tool or language?
      1 réponse
      6
      Expérience positive
      Entretien moyen

      Candidature

      J'ai passé un entretien chez Intel Corporation (Bengaluru)

      Entretien

      Coding related questions Project questions Logical questions Resume go through Sv uvm que Overall good experience working in intel Good company to work Constraint que, driver , monitor, scoreboard que

      Entretien pour Design Verification Engineer

      27 mars 2026
      Employé (anonyme)
      Offre acceptée
      Expérience positive
      Entretien difficile

      Candidature

      J'ai passé un entretien chez Intel Corporation

      Entretien

      the process was straight forward. one phone call to see if we align, followed by one screening interview for one hour video call/screen share for coding. then a panel with 4 interviewers.

      Questions d'entretien [1]

      Question 1

      They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
      Répondre à cette question

      Entretien pour Design Verification Engineer

      30 déc. 2024
      Employé (anonyme)
      Offre acceptée
      Expérience positive
      Entretien difficile

      Candidature

      J'ai postulé en ligne. J'ai passé un entretien chez Intel Corporation

      Entretien

      Need to have good digital system experience. State Machines, logic gates, programming. Language is verilog. They will ask what kind of project I did before. You will need to promote yourself on your technical capabilities and demonstrate a good attitude.

      Questions d'entretien [1]

      Question 1

      What I know about verilog
      1 réponse