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      Entretien pour ASIC Design Engineer

      13 août 2011
      Candidat à l'entretien anonyme
      Folsom, CA

      Autres retours d’entretien d’embauche pour un poste comme ASIC Design Engineer chez Intel Corporation

      Entretien pour ASIC Design Engineer

      8 févr. 2020
      Candidat à l'entretien anonyme
      Vancouver, BC
      Aucune offre
      Expérience négative
      Aucune offre
      Expérience neutre
      Entretien facile

      Candidature

      J'ai postulé en ligne. Le processus a pris 2 semaines. J'ai passé un entretien chez Intel Corporation (Folsom, CA) en juil. 2011

      Entretien

      I was contacted by email for phone interview for a senior ASIC Design Engineer position. The phone interview went alright (took place for about an hour and 20 mins). The interviewer was nice and asked me many technical questions which I answered. At the end of the interview he asked me when I can appear for an on-site interview. So.. I went for an on-site interview about 10 days later. This on-site interview process was the part that seemed very strange (and also not right) to me. It turned out that they call a whole bunch of candidates for interview on the same day. There are two batches of interviewees - morning and afternoon. I was selected for the morning batch (starts at 9am). The first half hour was a presentation about the group. It had all the candidates sitting together. Now most of these candidates were RCGs. I think I was the only senior level person in that group. After that the interviewees had 4 rounds of interviews, each for 45 mins. I was very surprised that every single of those 4 interviews for me were conducted by VERIFICATION (not DESIGN) engineers and most questions were on verification. The questions were not difficult enough. It seemed to me that those questions were prepared with the RCGs in mind. I had no problem in answering them. In any case, all the interviewers were nice and friendly. However, every single one of them asked me what kind of position I am interested in - design or verification. Now, my resume said very clearly that I am a design engineer and looking for similar position - so I didn't really understand the reason for ambiguity. After the technical interviews were over at noon, the candidates had to come back to the same conference room. We were told to help ourselves for lunch with some food that was waiting for us in the same room. No going out for lunch or anything. The food (very few items, I could just have salad and breads) was poor. Never before have I seen a company doing this to interview candidates. The whole setup seemed very unprofessional. What is even more ridiculous is that I did not even get to meet the hiring manager for the position. Come on... what is the point of an on-site interview then? About 3 business days later I got an email that I was not selected. I was a bit disappointed because I don't think I did badly in the interviews, however I wouldn't call it a huge surprise either going by the unprofessional and wrong interview process. When I am not even questioned on the area of work for the opening, that certainly raises questions about the fairness and credibility of the interview and selection process.

      Questions d'entretien [1]

      Question 1

      Mostly RCG level questions.
      Répondre à cette question
      Entretien difficile

      Candidature

      J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 jour. J'ai passé un entretien chez Intel Corporation (Vancouver, BC) en janv. 2020

      Entretien

      Sent resumé and cover letter via school co-op program. Got an email from co-op to meet at the office down by Marine-Gateway. There will be two interviewers and a bunch of questions about cover letter and resumé

      Questions d'entretien [1]

      Question 1

      How to make an AND gate with only XOR gates
      1 réponse

      Entretien pour ASIC Design Engineer

      19 août 2019
      Candidat à l'entretien anonyme
      New Delhi
      Aucune offre
      Expérience positive
      Entretien moyen

      Candidature

      J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Intel Corporation (New Delhi) en août 2019

      Entretien

      Resume Shortlisting process then took three round of technical interview and last is HR round that is just formality.Intel college interview process is totally depend upon luck those who went first in interview and if he is able to perform average then also he is able to get an offer.

      Questions d'entretien [1]

      Question 1

      Can u draw mod-6 down counter.Write design flow of ASIC,difference between $display,$strobe,$monitor.
      Répondre à cette question

      Entretien pour ASIC Design Engineer

      7 janv. 2020
      Employé (anonyme)
      Vancouver, BC
      Offre acceptée
      Expérience positive
      Entretien moyen

      Candidature

      J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 3 jours. J'ai passé un entretien chez Intel Corporation (Vancouver, BC) en mai 2019

      Entretien

      Was a 2 on 1 interview where they mostly asked about basic language knowledge on object oriented languages. Questions were based on whether you knew the terminology or not.

      Questions d'entretien [1]

      Question 1

      How do you access a private variable in a public class from another class in java.
      Répondre à cette question