J'ai postulé via la recommandation d'un employé. J'ai passé un entretien chez Intel Corporation (Folsom, CA) en mai 2026
Entretien
initial 30 minute phone interview, then a technical round around design and another round around verification. During the technical rounds they will ask you about your resume in relation to the topic of the round. Then they will ask questions in regards to hypotheticals and "digging deep". Know Computer Architecture, Memory systems, data structures, Big O Notation, verification methodology (UVM and systemverilog layout), digital design (FSMs, how to design a block) and Verilog trivia ($monitor, nonblocking vs blocking, timestamps, etc.)
Questions d'entretien [1]
Question 1
MESI Protocol
FIFO Verilog and condition for full and empty
Build FSM for 20 story building elevator (you have control in elevator and controls on every floor and discuss what floors take priority
Build a clock divider to take 2MHz signal to 1MHz
Build a 4:1 MUX using behavioral verilog than structural verilog
Tell me how many bits per tag, offset, and addr based on cache structure (1MB 8 way associative)
Tell me 5 stage pipeline
Tell me about different hazards and explain types of data hazards
how would you go beyond 5 stage pipeline
For me, these were 2 student interviews with 2 interviewers for different teams. They were nice and the questions weren't too difficult. If you prepare well, you can succeed! Make sure you repeat all the basic concepts.
J'ai postulé en ligne. Le processus a pris 1 jour. J'ai passé un entretien chez Intel Corporation en oct. 2023
Entretien
It is very simple process, You just have to get the right HR for hiring team and then they will guide you. You can search them on Linkedin, just search for verification jobs.
Questions d'entretien [1]
Question 1
Write system verilog code for Monitor to monitor and check the transactions from memory.