the interviewer was late for 1.5hour, asking basic synchronization technic and requiring hand writing Verilog code for a FSM described by him. Also talked about the FPGA related project in my CV

Completed within one day. Four steps. Only the first and last one was about the project I have done. Only the first and last one was about the project I have done, and just showed them the structure of my project and they asked me some details.