Format: Online test or phone screening Focus Areas: Digital design fundamentals (MUX, FSM, timing) Verilog/SystemVerilog syntax Basic assertions and testbench concepts Aptitude or C programming (occasionally) SystemVerilog constructs: always_comb, interface, modport, virtual, constraint, randc UVM architecture: agent, driver, monitor, sequencer, scoreboard Functional coverage, assertions (SVA), and constrained-random testing Debugging waveform scenarios