Phone interview was scheduled through Email, asked basic Verilog question. Then I was called for an onsite. Received Offer after 2 days. Important topics: Writing Synthesizable Code Understanding ASIC flow. Assertions. How do to debug a design.

2 phone interviews - One purely technical with 3 members and one was a discussion with the Manager. Technical interview was based on Physical design including explaining the PD flow, about clock trees and techniques adopted to avoid SI and also about technology nodes.