Within the VLSI team, your responsibilities will be to specify, design, implement and verify various digital blocks linked to Sequans’ next chipsets generation. You will work closely with our software, signal processing algorithms, architecture, integration and verification teams and you will be responsible for planning, tracking and reporting activities related to the implementation of your digital blocks.

RESPONSIBILITIES:

• Design (RTL coding) of key digital building blocks.
• Requirements analysis and micro architecture (uarch) definition.
• Design optimization in the context of timing, power and area.
• Contribute to top-level integration, testing and debugging.
• Planning, Tracking and reporting of key activities.
• Preparing documentation and technical reports.
• Supporting verification and debugging.
• Third party IPs evaluation.

EXPERIENCE AND SKILLS:

• Degree (BSc/MSc/PhD) in computer science, electrical engineering or equivalent studies.
• At least 5 years of working experience in ASIC and/or FPGA development.
• Strong command of hardware description languages (SystemVerilog/Verilog/VHDL).
• Background in optimization techniques for high throughput, low area, low power designs.
• Experience in multiple clock domains architectures.
• Experience in Front End activities (e.g Lint, CDC, RDC tools).
• Familiarity with Unix environment and shell programming/scripting (C-Shell, Tcl, Python).
• Experience in version control systems (Git, SVN).

BONUS SKILLS:

• Knowledge of synthesis and static timing analysis tools.
• Knowledge of Place and Route.
• Experience in implementing digital signal processing blocks.
• Experience in 3rd-Party IPs integration (NoC, RISC-V, memories, peripherals, etc).
• Exposure to LTE-M/NB-IoT, 4G LTE Cat 1bis, 5G NR.

PROFILE:

• Fast learning capabilities, highly motivated, self-starter, autonomous
• Ability to work in a fast moving and multicultural environment
• Team player, commitment & customer focus
• Excellent written and oral communications skills, fluent English