How is processor performance affected when the instruction cache hit latency increases? How do you overcome that?

Question

Tianlun · Accepted Answer

1. Use small, simple cache
2. Split & multi-banked cache organization (instruction cache and data cache)
3. Use virtual indexing and physical tagging rather than virtual address to reduce the time caused by translations.
4. Use way prediction to predict the index
5. Pipeline the write operation, do write the word to block and cache in background

Roopa · Answer

latency could increase with increase in cache size, one way to overcome could be to use a multi-level cache, so that L1 cache could be smaller and which decrease s hit latency

ZS · Answer

Increase in cache latency makes a longer pipeline and increases taken branch penalties. Using branch prediction helps reduce this affect.

Prathyusha · Answer

I don't think prefetching will help reduced "hit latency". Prefetching helps eliminate compulsory misses but to decrease hit latency, it should probably be at the lower levels of abstraction - circuit level.

Prathyusha · Answer

I don't think prefetching will help reduce "hit latency". Prefetching helps eliminate compulsory misses but to decrease hit latency, it should probably be at the lower levels of abstraction - circuit level.

Bill · Answer

I assume by 'overcoming' they mean that it cannot be improved by adding levels of cache hierarchy.  In that case I think they are looking for a prefetching scheme.

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