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Questions d'entretien pour Verification Engineer partagées par les candidats

## Principales questions d'entretien

Trier: Pertinence|Populaires|Date
On a demandé à un ASIC Verification Engineer...9 septembre 2010

### You have 2 pieces of rope, each of which burns from one end to the other in 30 minutes (no matter which end is lit). If different pieces touch, the flame will transfer from one to the other. You cannot assume any rope properties that were not stated. Given only 1 match, can you time 45 minutes?

48 réponses

Make a T. Simple

Take one rope (Rope A), place it down as a circle. Light match and start burning rope A at the tips that are touching. When the rope completely burns out, 15 minutes will have passed (since both ends are burning and being consumed at once). Hold the second rope (Rope B) straight and place one end so that it will immediately catch fire when the two burning points from (Rope A) finally touch and are just about to burn out. Thus 15 minutes on Rope A + 30 minutes on Rope B gives you 45 mins. Moins

** You cannot assume any rope properties that were not stated Burn like this *-------- ===&gt; After 30mins, Rope A finished burning, and both ends of Rope B start burning Moins

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### PHONE : 1. Pass by value/ pass by reference. Write a function to swap 2 variables - ll u use pass by value or reference ? 2. Do the same to swap 2 objects (how does it change) 2. Detect 11010 sequence with moore and mealy state machines. 3. Use of const ? What ll happen if you declare above 2 objects as const. 4. Explain NB assignment and blocking assignment. About event regions. 5. Fibonacci -- iterative solution and recursive solution. 6. Disadvantages of a recursive solution. 7. Output of this code fragment : reg a,b,c,d,w; assign w = a; initial begin a = 2; c=5; b<=c; a=5; end what is output of all registers. 8. Explain RISC pipeline. What is the problems. 9. Explain about uvm driver etc. ONSITE : round 1: Round Robin Arbiter Design round 2 : (1) Given a stack class implementation (LIFO) - there are 3 methods - push(), pop(), isempty(). Write a class using objects of given class to implement a FIFO. (2) Make best performance Implement the dist functionality in c++. Given a set of weights mimic to provide randomization skewed to the specification (Basically, write a function that would do something similar to a 'dist' in system verilog). round 3 : Given a divide by 3 state machine. Implement a divide by 5 statemachine. How many vectors are needed to verify it. So the circuit takes serial bit inputs and asserts if the number is a multiple of 3 or 5. round 4 : Circuits project. Basic pipeline architecture. Design a pipeline for a histogram processor. In every cycle we get an instruction (CLR, ADD INCR). Handle dependencies using bypass. round 5 : Given a producer and consumer. They are clocked with the same clock. Producer produces 80 writes for 100 clocks (no random). Consumer reads 8 times per 10 clocks. Find the FIFO depth. Write RTL and verify.

8 réponses

Is the histogram processor similar to MIPS or RISC processor, I think histogram is very specific to GPU application? Moins

It need not add up to 1. In system verilog, typical use of dist does not constrain this. It can be 60:60:60 -- which means probability of 1,2, 3 is 1/3rd. Moins

The histogram processor is something custom. It could be correlated to the DLX pipeline because of memory bottlenecks and dependencies. Moins

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### Create a 8 input AND gate using 3 4:1 muxes

8 réponses

Without an enable bit on at least one of the mux's the maximum inputs would be 7. Moins

I don't see it being possible with three standard 4-1 muxes... Using 4, this question is straight forward... The two selects of each mux are your 8 inputs... tie out put of each mux to the (11) case input to the mux. Moins

We need 3 4:1 MUX and a And gate. Are we allowed to use 'and' gate?

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### Describe a function to check if an integer is a power of 2.

6 réponses

Write the number in binary and count the number of ones in that.If the number os ones is only 1 then it the number is indeed a power of 2 Moins

For an integer n: If n is less than 1, return false. If the bitwise &amp; of n and n-1 is 0, return true. Otherwise, return false. Moins

I think the main idea is to use recursion function, for the integer which is larger than 0, if it is 1 return true, else return function(n-1) Moins

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### You have seven stones and a weighing scale. Six of the stones are equal in weight and one is lighter. How will you figure out which one is lighter ? Minimum tries required to do so ?

5 réponses

Needs two weighing at most: 1. Put {1, 2, 3} on LHS and {4, 5, 6} on RHS. 2. If LHS and RHS are equal 7 is the lighter one. else discard heavier of previously weighed group. Now we have a group 3 stones left. Lets call them A, B, C. 3. Put A on LHS and B on RHS. 4. If LHS and RHS are equal C is the lighter one. else lighter or LHS or RHS is the lighter one. Voila! Moins

Two tries. 1st try: 3 : 3, 7th is fake if equal; otherwise, 2nd try: 1:1 picked from the light triple in 1st try. the lighter one is fake if any, the third one fake otherwise. Moins

Trail 1: At random weigh two stones vs. two stones (3 sitting on the side) A: Of the 4 on the scales if one side weighs more then the other then weigh one on each side (since one of them must be heavier) B. If the 2 vs 2 are equal then at random weigh 2 (one on each side) of the three left on the side. If they are the same then the 3rd one that never got weighed is the heaviest. Simple case of process of elimination by grouping (Divide and Test) Moins

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### how to find the second smallest number out of iven n integers

5 réponses

No, you need to also check for the second_smallest as well. For instance your code does not work for the sequence of "10,20,15". Moins

You can do it in O(n); for(i=0 ; isecond_small) continue; else { if(a[i]&gt;small) second_small = a[i]; else { second_small = small; small = a[i]; } } } } Moins

Quick select

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### How would you verify a 3 bit and 64 bit adder? Would you adopt the same strategy?

4 réponses

Will verify all cases for 3 bit- 2^3*2^3 Whereas will only overify corner cases for 64 bit adder Moins

by writing coverage, adder 3-bit we have to check the upper case and lower case ,and same 64 bit also we have to check the lower case as well as upper case and then cross 3 bit and 64 bit. Moins

full scan and partial scan

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### is run phase top down/bottom up

4 réponses

All UVM phases are bottom-up except the build phase which is top down (because the parent components have to be constructed already when the child components are built). Moins

Neither bottom up nor top down The run phase tasks of all UVM components run in parallel Moins

None

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### Describe a circuit that implements the following truth table using only NAND gates. A B OUT 0 0 1 0 1 1 1 0 0 1 1 1

4 réponses

out = (A NAND (B NAND B))

OUT = (A NAND (B NAND 1)) or out = (A NAND (B NAND B)) like what anonymous said. Moins

out = ((A NAND A) NAND (A NAND A)) NAND (B NAND B)

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### Questions were asked on verilog and system verilog. Some famous puzzles and aptitude questions were asked. In manegerial round my errors of written round were discussed.

3 réponses

Answer with confidence. Show the attitude of learning new things. Show genuine interest about the role. Moins

Hi, Could you please tell me what was the section-wise break up of the number of questions. Moins

And a few topics covered in analog and digital which you remember

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